1. Field of the Invention
The present invention is related to the testing of integrated circuits (ICs), including IC built in self tests (BISTs).
2. Description of the Related Art
Signature circuits are frequently used for detecting faults in integrated circuits. Test vectors are applied as test inputs to a circuit under test (CUT) or device under test (DUT). The monitored signals of the CUT are provided as inputs to a signature circuit. A conventional approach is to combine the monitored signals from the CUT with a stored value of the signature register (a “current” value) to create a new signature register value for each test vector is applied to the CUT. At the end of the set of test vectors, the contents of the signature register (i.e., the “signature”) is compared to an expected signature for a fault-free circuit, which is typically calculated via a simulation. Fault coverage varies depending on the test vectors, the number of test vectors, the efficiency of the signature circuit, and the like. The percentage of fault coverage is the percentage of the total number possible single faults for which the resulting signature is different from that of a fault-free circuit. For example, the data, address, and control signals of a data bus in the CUT can be monitored as inputs for the signature circuit.
The combining of a monitored signal with a prior signature register value typically includes a mathematical operation. If multiple signals from the CUT are simultaneously provided as inputs to the signature register, the signature register is typically referred to as a Multiple Input Signature Register (MISR). One mathematical operation used with a MISR maintains a running odd-parity in each bit of the signature register of corresponding CUT signals. Other techniques combine multiple input signals and multiple signature register bits in some linear combination to create the next MISR state.
Generally, the greater the complexity of this operation, the better the fault coverage. More complex operations, however, can place limits on the speed at which the test vectors can be run. For example, each increase in the depth of the logic used to generate a new Multiple Input Signature Register (MISR) value increases the propagation delay to the input of the MISR's register. Also, if a circuit under test (CUT) signal is used as an input to multiple gates within the MISR, the MISR's multiple gates increase the capacitive load on that CUT signal with a corresponding decrease in the speed at which the CUT can operate, even under normal (non-test) operation. Hence, desirable considerations of MISR design include to achieve a high degree of fault coverage with a relatively small number of test vectors, to run test vectors at a relatively high clock rate, and to load the CUT lightly such that the CUT's performance is unimpaired during normal (non-test) operation.
Another consideration for Multiple Input Signature Register (MISR) design is that the larger the MISR circuit, the greater the likelihood of the MISR circuit's own susceptibility to faults. The can result in a decreased yield of otherwise good ICs due to faults occurring within the MISR. Of course, larger MISR circuits also increase the die size of the IC, which also impacts cost. For these reasons, the smaller the MISR circuit, the better.
Conventional Multiple Input Signature Registers (MISRs) perform a linear operation on a combination of the inputs to the MISR and the MISR's current state values to create the next MISR state. In the art, MISRs are also referred to as signature space compactor circuits since MISRs produce a signature with relatively few bits at the end of many test vectors rather than having, for example, a different signature per test vector. This should not be confused with compactors used to compress the size of a test vector generator circuit or ROM table.
One conventional space compaction technique uses multi-level logic that combines the monitored circuit under test (CUT) signals to form a single bit value per test vector. The signature is the resulting stream of values (which may then undergo additional compaction through a “time compaction” circuit such as a run-length coder such as a Ziv-Lempel code). See K. Chakrabarty and J. P. Hayes, “Test Response Compaction Using Multiplexed Parity Trees,” IEEE Trans. Computer-Aided Design, vol. 15, pp. 1399-1408, November 1996.
According to one conventional Multiple Input Signature Register (MISR) technique, the signals from the circuit under test (CUT) are provided as inputs to logic that combines these signals with one of the current MISR register outputs. See U.S. Pat. No. 5,938,784 to Kim, in which a single register output of the MISR is fed back to create a primitive polynomial generator.
Another example is shown in FIG. 10.17 of M. Abramovici, et. al., Digital Systems Testing and Testable Design, Computer Science Press/W.H. Freeman, New York, N.Y., 1990, pp. 446. FIG. 1 illustrates such a MISR with Di representing the data inputs to the MISR from monitored signals of the CUT, and Ci representing coefficients of a generator polynomial. The “+” in FIG. 1 indicates an exclusive-OR (XOR) operation. The coefficients Ci operate such that a connection is provided when Ci=1 and no connection when Ci=0, i.e., logical ANDing by Ci. An output of a single register, the right most register (D-type flip-flop) in FIG. 1, is provided as an input to the logic gates implementing the generator polynomial, and the result is XOR'd with the monitored signals. One disadvantage to this approach is that the register driving the logic gates for the generator polynomial is loaded relatively heavily, which can slow down the rate at which the signature circuit operates. Abramovici notes that the probability of an undetected fault is 2−n for an n-bit MISR.